This invention relates to a semiconductor device comprising a plurality of MOS transistors with high performance and high reliability, in which an amount of leakage current flowing through the junction between source and drain regions and a substrate is small.
In recent years, a single drain structure has been widely used in the field of a MOS transistor. In this structure, a gate electrode is used as a mask in the ion implantation process for forming the source and drain regions immediately after the forming of the gate electrode. FIG. 1 shows the sectional view of the single drain structure. In the drawing, 1 denotes a silicon substrate, 2 denotes a gate insulator film, 3 denotes a gate electrode formed from polysilicon, and 8 denotes source and drain regions formed to have high impurity concentration in the ion implantation process using the gate electrode 3 as a mask.
With such a structure, however, the punch-through phenomena may occur or hot carriers may be generated at the drain edge if the MOS transistor is miniaturized for attaining high speed operation and high integration level. When such phenomena occur, the performance of the transistor may be degraded.
In order to solve this problem, various double drain structures such as a lightly doped drain structure (hereinafter referred to as an "LDD structure") shown in FIG. 2 have been proposed. These methods are employed as a mainstream in the present time, in which source and drain regions are formed after forming a side wall surrounding the gate electrode.
According to these methods, after a gate electrode 3 is formed from polysilicon, the shallow ion implantation is performed to form LDD source and drain region 5, as indicated by a real line and a broken line in a silicon substrate 1 of FIG. 2. Next, the side wall 12 formed of an insulator film is provided on the polysilicon gate 3. By using the gate side wall 12 as a mask, the deep ion implantation is performed in the source and drain regions 8 to obtain a MOS transistor having the LDD structure.
Also in the conventional self-aligned silicide (hereinafter referred to "SALICIDE") process wherein refractory metal silicide is formed on the gate electrode 3 and the source and drain regions 8 in a self-aligned manner, the side wall 12 is formed on the gate electrode prior to the forming of the silicide, and then impurity ions are implanted in the gate electrode 3 and the source and drain regions 8 simultaneously.
Both in the LDD structure process and the SALICIDE process, the ends 8a of the source and drain regions 8 having high impurity concentration and deep junction depth, which are located below the gate electrode 3, are not located near the edge 3a of the gate electrode 3 but near the edge 12a of the side wall 12, prior to the heat treatment for impurity activation.
FIG. 2 shows the view of the transistor after the heat treatment. In the drawing, in which the edges 8a located below the gate electrode extend under the side wall 12. As a result of the heat treatment for impurity ions activation, the impurity implanted into the source and drain regions 8 laterally diffuse, and the edges 8a are shifted to the positions shown in the drawing. Immediately after the ion implantation, the edges 8a are adjacent to the edges 12a in the vertical direction to locate the gate insulating film 2 therebetween.
In the forming step of the source and drain regions 8 with high impurity concentration using the side wall 12 formed on the gate electrode 3 as a mask, the crystal structure of the silicon substrate 1 at the source and drain regions 8 is damaged by the implanted high concentration impurity ions, to form an amorphous silicon. While, the portions covered with the side wall 12 are not turned into amorphous silicon, and thus the boundaries between the amorphous silicon and the single crystal structure in the substrate 1 are formed at the portions located below the edges 12a of the side wall surrounding the gate.
After the impurity implantation, the heat treatment for the impurity activation and the recrystallization of the substrate are performed. In this time, if the thermal expansion coefficient of the material used for the side wall is so different from that of the substrate, the stress due to the difference in the thermal expansion coefficients may be applied to the substrate by the side wall, thereby the recrystallization of the substrate located below the side wall edge 12a may be prevented. As a result, defects are generated in the substrate at the junction between the source and drain regions and the substrate, i.e., at the edges 8a located below the side wall edge 12a, and a leakage current will flow through the junction. When the leakage current is extremely large, the MOS transistor may not operate.
In this time, the annealing of the defects, i.e., the perfect recrystallization of the substrate in the amorphous state can be attained by performing a heat treatment at a temperature as high as 1000.degree. C. over one hour. Due to the heat treatment, however, the doped impurities are extensively diffused, and the desired impurity profile cannot be easily obtained. As a result, the MOS transistor does not operate with high performance.